Checking system



United States Patent Ofiice 3,358,203 Patented Feb. 6, 1958 3,368,203CHECKING SYSTEM Edward Loizides, Ponghkeepsie, N.Y., assignor toInternational Business Machines Corporation, New York, N.Y., acorporation of New "ark Filed Dec. 23, 1963, Set. No. 332,777 7 Claims.(Cl. 340-1725) The invention relates to checking systems and more particularly to apparatus for checking the operation of a recirculatingmemory.

In the data handling art recirculating memories are utilized for storingdigital information and making this information available at a latertime. A recirculating memory may comprise, for example, a recirculatingdelay line, a magnetic drum, or an endless loop of tape. In arecirculating memory it is necessary to provide some means foridentifying particular bits of information stored within the memory.Usually the memory is divided into unique time intervals by a timingcircuit. Thus bits of information are sampled at particular timeintervals in order to synchronize the data stored within the memory withexternal utilization apparatus. If the timing circuit fails, theuniqueness of the time intervals is lost, effectively resulting in theloss of stored information. A checking scheme which merely checks theoperation of the timing circuit is not sutlicicnt to check arecirculating memory. Any one of a number of circuits may cause thedestruction of information. The failure may result in sense amplifierswhich read out of the memory, driving circuits which read into thememory, or the memory itself may fail or distort the information so asto cause a loss of synchronization.

It is therefore an object of this invention to provide an improvedrecirculating memory.

It is a further object to provide improved apparatus for checking atiming circuit associated with a recirculating memory.

It is also an object of this invention to provide checking apparatuswhich will check all of the logic in addition to the timing circuitsassociated with a recirculating memory.

It is a still further object of this invention to provide a self-checkedsynchronizing apparatus for a recirculating memory.

The above objects are accomplished in accordance with the invention byproviding a timing circuit which is synchronized with recirculating databits stored in a recirculating memory. Check bits corresponding to timesindicated by the timing circuit are stored in the memory between groupsof data bits. Checking is accomplished by comparing the check bits readfrom the memory with the actual times indicated by the timing circuit.If there is disagreement, the timing circuit is not properlysynchronized and the unequal comparison causes an error signal to begenerated.

The invention has the advantage of serving not only as a timing circuitcheck, which most apparatus have, but also as a check of therecirculating storage itself, and all circuitry associated therewith.Further, apparatus constructed in accordance with the invention willdetect errors caused by distortion in the signal read from therecirculating storage.

The invention has the further advantage of flexibility in that thecircuitry may be easily varied in accordance with the size of therecirculating memory and the size of the timing means.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawmgs.

In the drawings:

FIG. 1 is a block schematic diagram of a recirculating memory in whichthe invention is embodied; and

FIG. 2 is a timing chart which illustrates the relative voltagepotential of various points in the circuit of FIG. 1.

Referring now to FIG. 1, a storage medium 10 is providcd which may be adelay line memory, a track on a magnetic drum or disc, a shift register,or a similar recirculating storage device. A sense amplifier 12 isprovided at the output of the storage medium 19 for amplifying,stretching and shaping signals read from the storage medium 10. Theoutput 14 of sense amplifier 12 is fed back to an AND circuit 16, theoutput 18 of which drives an OR circuit 20. The output 22 of the ORcircuit 20 is fed to a driver 24 which provides an input 28 to thestorage medium 10.

A basic timing oscillator 39 is provided which generates pulses at afixed rate at its output 32. The oscillator drives a binary counter 34having L lower order stages and H higher order stages. In the embodimentshown, a five-stage (T1, T2, T4. T8, and T16) binary counter isemployed, but it should be understood that the number of stages isillustrative only and may be varied to adapt to any error checkingscheme desired. The outputs 36, 38 of T1 feed AND circuits 40 and 42respectively. The outputs 44 and 46 of the higher order stages T8, T16drive the other legs of the AND circuits 40 and 42. The outputs 43, St)of the AND circuits 40 and 42 are ORed together by OR circuit 52, theoutput 54 of which is fed to AND circuit 56. The outputs 58, 60 of T2and T4 are fed to AND circuit 62, the output 64 of which gates ANDcircuit 56 and feeds inverter 68. The output 70 of AND 56 labeled checkbit feeds one leg of exclusive OR 72, the other leg of which is fed bythe output 14 of sense amplifier 12. The output 74 of exclusive OR 72gates AND 73, the output of which indicates an error condition.

The output 32 of oscillator 30 drives timing circuit 34 and a so feedsinverter 82. The inverted output 84 of the oscillator gates AND circuits86, 88, 16, 99, and provides error sample to AND 78. The AND circuits86, 88, 16, and are also energized by the following input lines: datainput line 92: synchronize line 94; regenerate line 96; and read outline 98. The synchronize line 94 is inverted by inverter 100, the output102 of which disables AND circuits 85. I6, and 78. The output 14 ofsense amplifier 12 energizes AND circuit 16 and AND circuit 99 whichprovide respective y, a regenerate input 18 to storage 10 and an output104 to be utilized by external apparatus:

The outputs 108, of AND circuits 86 and 88 feed OR circuit 20 whichprovides access to the storage medium 10.

Referring to FIG. 2, the operation and relative timing within the systemof FIG. I will now be described in detail. Curve A illustrates theoutput 32 of oscillator 30. The negative going portions are labeled fromZero to 31 and correspond to times at which the error sample, theinverted output of oscillator 30, is taken (see also curve K). CurvesB-F correspond to the outputs of triggers T1, T2, T4, T8. and T16 ofcounter 34. The counter is stepped on the positive going portion ofoscillator output 32 and the triggers are connected to count in binarycoded ecimal. Curve G illustrates the output of OR circuit 52 and isobtained by ANDing together the complements of curve B and curve E.Curve H corresponds to the output of AND 62 and is obtained by ANDingtogether the complements of curves C and D. Curve H defines the periodin which the check bits are generated as will he subsequently described.Curve I illustrates the check bits generated at the output of AND 56.Curve J represents the shaped 3 storage contents of the data read bysense amplifier 12. A unique scheme is employed for gating the H checkbits into storage at the proper times in the timing cyc e. The bitscorresponding to the states of T16 and T8 are Data is read into thestorage medium by energizing data input line 92 during data bit times ina character cycle. If data input line 92 is energized an oscillatorpulse on line 54 causes a binary one to be written into the storagemedium via AND circuit 815, or 29 and driver 24. At all gated intostorage at check bit times. 0. 1; 8, 9; 16, 17', 24, and 25. The lowerorder stages T1, T2, and T4 are eonother times when data input line )2is decnergized Zeros venientiy used to define the check bit times andcontrol are written into the storage medium. the generation of the checkbits. Data is read out of the storage medium by energizing Referring nowto the table below the various states of read out line 93. The shapeddata hits then appearing at the triggers Tl l'l corresponding to theactual count in the output 14 of sense amplifier 12 are sampied by thethe counter from O to 31 are illustrated. inverted oscillator outputline 84 to sample the data pulses Count T1 T '1, T T Count T1 T2 T4 T1T0;

tum-k Int 0 0 0 0 0 0 Chltk liit 10 0 0 0 0 1 Times. 1 1 U ll 1] I.)Times. 17 l (l U U 1 1mm mt. 2 0 1 0 0 0 11.011110. 1s 0 1 0 0 1 Times.3 1 1 t) (I I) Times. 1 1 l] 0 1 400100 00101 510100 -10101 0 0110001101 711100, 11101 1 11001111: s 0 0 0 1 0 i LiiitOk mi. 0 0 0 1 1Tani-s. 0 0 0 1 0 1 Times. 1 0 0 1 1 1mm ltit 10 0 1 0 1 0 Data Iiit 200 1 0 1 1 Times. 11 1 1 it 1 (1 Times. 1'7 1 1 ii 1 12 00110 as 001111310110 2010111 14 01110 3001111 15 1 1 1 1 0 a1 1 1 1 1 1 Examiningthis table. it is seen that only during check at their midpoint to thuscompensate for distortion. The bit times are T2 and T4 both zero. At allother times one output 104 of AND 90 then represents a train of zeros orthe other of these triggers is on. Further, T1 is in and onescorresponding to the data stored in the storage the zero state for thefirst check bit time of each character, medium. The bits stored in thestorage medium are connnd in the one state for the second check hit timeof each tinuously recirculated in order that the check bits willcharacter. The states of these triggers are utilized to not bedestroyed. This is accomplished by holding the gate out the check bitsin the following manner. The zero regenerate line 96 positive. In thismanner the output sides of T2 and T4 are ANDed together in AND 62. ofthe sense amplifier 12 is a lowed to pass through the Therefore, theoutput 64 ot AND (12 energizes AND 56 AND circuit 16 where it is gatedby oscillator pulses 84. only during check bit times, i.e. when T2 andT4 are both The output of AND circuit 16 passes through OR circuit zero.This is illustrated by curve H FIG. 2. The actual 20 and driver 24 inorder that the information may evenchcck bit value at check bit time isdetermined by the tually be reinserted into the storage medium 10. stateT8 and T16. T8 represents the first check bit and Assuming that thecounter and the information stored T16 represents the second check hit.T1 is used to control are in synchronism the foilowing sequence takesplace as the gating of these bits. Thus. when T1 is zero the firstillustrated by the timing chart of FIG. 2. The first charcheck bitcorresponding to the state of T16 is gated actcr read from the storagemedium 10 is character 1. through AND 40, via OR 52 to energize AND 56.The As illustrated by curve I of FIG. 2 the H hits associated output ofOR 52 is allowed through AND 56 only during with character 1 should read00. The shaped output 14 check bit times under control of output 64 ofAND 62. of sense amplifier 12 is illustrated by curve 1. At this When T1changes state the one output 38 gates the second time of the cycle,illustrated by curve A, the shaped outcheck bit corresponding state ofT8 through AND 42. put 14 of sense amplifier 12 (curve J) is comparedwith Thus, the heck bits are defined by the state of the higher theactual state of the counter 34 on line 70 (curve I). order stages T8 andT16, and are generated at proper At time zero FIGURE T1 is in Zerostatus, so that the clock times under control of the lower order stagesT1, output of T16 is gated through AND circuit 42, OR circuit T2 d T4,38, to Exclusive OR 32. Thus, the value of the count of Synchronismbetween the delay line and the counter is the storage means Which wasstored in the memory as initially obtained by energizing the synchronizfi 94 check bits is compared with the actual decoded count for one fullcycle of the timing circuit 34. This a lows the f the c unter on line70. The two should compare, and check bits generated at the output ofAND circuit 56 to give no output at the Exclusive OR 72. The positivegob gated b h b i ill 131113133 th o h AND ing portion of the oscillatorwave form shown in curve circuit 88, OR circuit 20 and into the thestorage medium A fo g i e 0 changes trigger T1 to the one state. 1!].Curve I illustrates the Wave shape of the cheek hit The output 38 of T1therefore energizes AND circuit 42. lin 70, Si thi li i gated by the i td ill t At this time in the cycle of the counter. T16 is 011'. There-(mtput line 84 (10 prevgnt slivgrg f 'gm im dvgrtently p355- fore, theoutput 46 (iiStthlLS ll'lfi output Oi AND CifCllii ing through the ANDcircuit 88) the actual hit stored in 55 and Signal P115588 through ORCircuit 42 the storage medium 10 is only half the duration of a fulllhmllgh AND CiYCUit Thcfcforc the Check bit oscillator cycle. Thus, theoutput of the storage medium of EXclllivfi OR 72 remains negative andF10 error is t b h d b sense tifi 12 to t d h pulse indicated. Thestorage medium contents illustrated by period to a f ll ogcinator cycleas Shown i curve curve I at time 1 are also negative because no checkbit Th Synchronize li 94 i i t d to di bk; AND i 70 was prerecorded atthis time. Therefore the comparison uits 86, 16 and 78, preventsinadvertently p gsing Of the SiOlFlgC COl'IiSIlI with iiiC timeillCliCltlCd by the data on data input line 92 or regenerated data onregen- Connie? in Exclusive OR 72 mums in Output erate line 96 into thestorage medium. The synchronize f m. line inverted also prevents anyerror indications by dis- An analogous sequence takes place at check bittimes abling AND circuit 78. 8 and 9. At time 8 the cheek bit read fromstorage should be a 1 (curve I). The contents of counter 34 shouldgenerate a 1 on check bit line 70. If the memory is synchronized the twocompare and no error is indicated. However, should the counter be out ofstep and line 70 negative at this time, an output will occur fromExclusive OR 72. When the Exclusive OR is sampled at time 8 by errorsample 84 (curve K) an error signal will occur on line 80.

To summarize, the invention provides an improved checking circuit forchecking a recirculating memory which is synchronized by a timingcircuit. The invention comprises means for storing bits corresponding tocertain times indicated by the timing circuit at selected positions inthe memory between data bits. The stored times are then compared withthe actual times indicated by the timing means as the bits arerecirculated. Means are also provided for automatically synchronizingthe storage medium with the timing circuit should the synchronization belost.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from spirit and scope of the invention.

What is claimed is:

1. In a recirculating storage medium having a plurality of data bitpositions therein,

a reading station for reading data stored in said medium;

a timing means for generating timing pulses corresponding to hitpositions in said storage medium, said timing means comprising L lowerorder stages and H higher order stages of a counter;

means for decoding the outputs of said lower order stages;

means responsive to the decoded outputs for inserting the value of saidhigher order stages into bit positions of said storage mediumcorresponding to decoded times indicated by the lower order stages ofsaid counter;

comparing means for comparing the value of recirculated bits read fromsaid storage medium with the actual value of said higher order stages ofsaid counter at times indicated by the lower order stages; and

means responsive to an unequal comparison for indicating a lack ofsynchronism between said storage means and said timing means.

2. In combination with a recirculating memory:

a timing means for synchronizing data stored in said memory;

means for storing certain times indicated by said timing means atselected positions in said memory; and

means for comparing the stored times read from said memory with theactual times indicated by said timing means.

3. A recirculating storage medium having a plurality of bit positionstherein;

timing means for generating timing pulses corresponding to hit positionsin said storage medium;

means for inserting selected values of said timing means as check bitsin said memory; and

means for comparing the value of the check bits read from said storagemeans with the actual value of said timing means.

4. A source of timing pulses;

means for counting said pulses, comprising a plurality of countingstages;

a recirculating storage medium;

means for decoding the outputs of selected ones of said counting stagesto thereby generate timing signals corresponding to predeterminednumbers of said timing pulses;

means for gating said decoded signals into said recircu- ]ating storagemedium for storage therein;

means for reading said stored signals; and

means for comparing the stored signals during recirculation with thegenerated timing signals for a one-tonne correspondence.

5. A recirculating storage medium;

a timing circuit for synchronizing data read into and out of saidstorage medium, said timing circuit having a unique configuration ofstates for each interval of a timing cycle;

means for reading pulses representing a particular state of said timingcircuit into said storage medium at a predetermined interval to providecheck bits therein;

means for reading data from said storage medium;

means for comparing data read from said storage medium with pulsesrepresenting the state of said timing circuit at times when the storedcheck bits should appear at the output of said storage medium, and foremitting a signal when a comparison does not exist; and

means responsive to the output of said comparing means for indicating alack of synchronism between said timing means and said storage medium.

6. In combination with a serial cyclic memory system wherein informationbits are repeatedly circulated through said system at a predeterminedrate and are passed serially through a reading device once during eachcirculation,

timing means for synchronizing the information bits with the readingdevice;

means for generating check bits corresponding to certain times indicatedby said timing means;

means for storing said check bits in said memory system at predeterminedlocations therein; and

means for comparing the times indicated by said checking hits as readfrom the reading device with the actual times indicated by said timingmeans, thereby an equal comparison results if said timing means and saidmemory are in synchronism.

7. Apparatus for checking a recirculating memory comprising:

a timing means;

a check bit generating circuit responsive to said timing means forgenerating check bits synchronized with said timing means and having adiiierent configuration at different times in a cycle of said timingmeans;

means for storing said check bits in the memory at predetermined timesin a cycle of said timing means;

means for reading the recirculated check bits from the memory, and

means responsive to said generator and said reading means for comparingthe configuration of said stored check bits with the generated checkbits.

References Cited UNITED STATES PATENTS 11/1962 Schneider 340-173 10/1964Schwartz 34()-172.5

1. IN A RECIRCULATING STORAGE MEDIUM HAVING A PLURALITY OF DATA BITPOSITIONS THEREIN, READING STATION FOR READING DATA STORED IN SAIDMEDIUM; A TIMING MEANS FOR GENERATING TIMING PULSES CORRESPONDING TO BITPOSITIONS IN SAID STORAGE MEDIUM, SAID TIMING MEANS COMPRISING L LOWERORDER STAGES AND H HIGHER ORDER STAGES OF A COUNTER; MEANS FOR DECODINGTHE OUTPUTS OF SAID LOWER ORDER STAGES; MEANS RESPONSIVE TO THE DECODEDOUTPUTS FOR INSERTING THE VALUE OF SAID HIGHER ORDER STAGES INTO BITPOSITIONS OF SAID STORAGE MEDIUM CORRESPONDING TO DECODED TIMESINDICATED BY THE LOWER ORDER STAGES OF SAID COUNTER;